Conventionally known methods for manufacturing a silicon epitaxial wafer (hereinafter referred to as epitaxial wafer or just wafer) are to grow in vapor phase a silicon epitaxial layer (hereinafter referred to as epitaxial layer) on a main surface of a single crystal silicon substrate (hereinafter referred to as silicon substrate).
According to this manufacture of an epitaxial wafer, silicon source gas is supplied onto a main surface of a silicon substrate mounted on a susceptor in a reaction chamber with heating the silicon substrate, so that an epitaxial layer is grown in vapor phase.
In this manufacturing process of an epitaxial wafer, warping occurs in the silicon substrate due to the heating. For this reason, a susceptor on which the silicon substrate is mounted is provided with a pocket formed so as to coincide with the warping, and the silicon substrate is mounted onto a bottom face of the pocket. Besides this, various methods to suppress the warping have been proposed (for example, see patent documents 1 and 2).
In some cases, a mesh-like groove as a path for gas is formed on a face of such susceptors on which a silicon substrate is to be mounted. It provides advantages that a silicon substrate can be easily dismounted from the susceptor when removing it, as well as that a silicon substrate is prevented from displacement in mounting it. These susceptors used therein are normally made of graphite as its base and coated with silicon carbide coating. This is because graphite reacts with source gas so that the surface thereof changes to silicon carbide during a process of vapor phase growth. For this reason, they are coated with silicon carbide previously. The silicon carbide coating is normally formed by CVD (chemical vapor deposition method). When the above-mentioned mesh-like groove is provided on a face on which a silicon substrate is to be mounted, the silicon carbide coating is formed after the groove is processed, and thereafter a finishing polish is given to the face. However, if the face is polished excessively, there occurs a problem that a silicon substrate sticks to the susceptor (see FIG. 4B). In order to prevent this adhesion, it has been proposed a technique of allowing this face to have a surface roughness of 1 μm or more in average roughness and 10 μm or more in maximum roughness (for example, see patent document 3).
Patent document 1: Japanese patent publication No. 3900154
Patent document 2: WO2002/097872
Patent document 3: Japanese patent application publication No. Hei2-174116